PURPOSE: To attain high speed operation (processing) by providing a coefficient device multiplying a code length of a code not decreased and a coefficient decided as a source element of a source polynomial and the code length of the decreased code in advance as each coefficient of an error location polynomial.
CONSTITUTION: A code length (n) of a code not decreased and a coefficient α (n-n"+1)j decided by a code length n' of the decreased code are multiplied as each coefficient σ j of the error location polynomial obtained in advance by coefficient devices 41∼44 and its output is preset by plural m-bit parallel latches 1∼4. The (n'-1) times of shift is repeated by m-bit parallel latches 1∼4 from the preset state, all latch outputs and '1' are added by an adder 9 and its output is decided by an input zero decider 10. When the result of decision is zero, a code error takes place at the location of a received word and when the result of decider is not zero, no code error exists. Thus, the actual code error location is obtained from the error location number α -i obtained in this way, and the error number is obtained to execute the code error.